Microelectronic structures, and in particular semiconductor structures, include microelectronic devices such as semiconductor devices. The microelectronic devices are located and formed over a microelectronic substrate, such as a semiconductor substrate. The microelectronic devices are connected and interconnected using patterned conductor layers that are separated by dielectric layers.
In addition to the connection and interconnection of microelectronic devices within a microelectronic structure while using patterned conductor layers that are separated by dielectric layers, microelectronic structures, and in particular semiconductor structures, also frequently use through wafer (or substrate) via structures that provide an electrical connection from a top side to a bottom side of a microelectronic substrate, such as a semiconductor substrate.
Through wafer vias when used within microelectronic substrates may serve functions that include, but are not necessarily limited to, microelectronic substrate grounding functions and microelectronic substrate electrical biasing functions.
While through wafer vias within microelectronic substrates serve valuable functions, through wafer vias within microelectronic substrates are not entirely without problems. In particular, through wafer vias are often difficult to efficiently fabricate and effectively fill with a comparatively narrow linewidth (i.e., in a range from about 5 to about 0.1 microns), while substantially or completely penetrating through a microelectronic substrate having an increased thickness.
Various aspects of vias in general, potentially including but not limited to through wafer vias, are known in the microelectronic fabrication art.
For example, Jang et al., in U.S. Patent Application Publication No. 2001/0007797, teaches a method for forming a tungsten via over a titanium containing barrier layer within a contact aperture to form a contact structure within a semiconductor structure absent delamination of the contact structure. The method includes forming and annealing a tungsten seed layer, while using a fluorine containing source gas, over the titanium containing barrier layer prior to forming the tungsten via over the titanium containing barrier layer.
In addition, Lim in U.S. Patent Application Publication No. 2004/0115929, teaches a method for forming a tungsten via within a contact aperture within a semiconductor structure with enhanced step coverage. The method includes first forming within the contact aperture a tungsten nitride barrier layer while using an atomic layer deposition (ALD) method.
Further, Nishimura et al., in U.S. Patent Application Publication No. 2005/0023702, teaches a method for forming a tungsten via within a contact aperture within a semiconductor structure, absent a void within the tungsten via. The method includes a two-step deposition of the tungsten via, where the crystal grains within the tungsten deposited within the first step are 30 nm or less.
Still further, Ogasawara et al., in U.S. Pat. No. 6,943,109, teaches a method for forming a tungsten via within an aperture within a semiconductor structure with comparatively low resistance and high reliability. The method includes treating the aperture with a fluorine containing gas prior to filling the aperture with the tungsten via.
Still yet further, An, in U.S. Patent Application Publication No. 2006/0046456, teaches a dual damascene method for forming a dual damascene structure with enhanced performance within a semiconductor structure. The dual damascene structure includes a tungsten via within a via portion of the dual damascene structure and a copper interconnect within an interconnect portion of the dual damascene aperture.
Yet still further, Tanaka, in U.S. Patent Application Publication No. 2006/0046457, teaches a method for forming a tungsten via within an aperture within a semiconductor structure. The method uses a post deposition purge of fluorine from a tungsten via deposited using a tungsten fluoride deposition material.
In addition, Jung et al., in U.S. Pat. No. 7,022,601, teaches a method for forming a tungsten via within an aperture within a semiconductor structure absent of defects. The method uses a barrier layer comprising a tungsten-silicon-nitride material deposited prior to the tungsten via.
Finally, Zhu et al., in U.S. Patent Application Publication No. 2006/0252252, teaches a method for forming a contact layer contacting a tungsten via with enhanced performance within a semiconductor structure. The method provides for first cleaning a tungsten oxide from the tungsten via prior to forming the contact layer contacting the tungsten via.
The use of through wafer vias is likely to be of continued prominence and importance as microelectronic device and microelectronic structure dimensions decrease, and as microelectronic circuit functionality and performance requirements increase. To that end, desirable are through wafer via structures having enhanced performance, and methods for fabricating those through wafer via structures. In particular, there is a need for providing a method that can be used to optimally fill through wafer via structures with a conductive metal, such as tungsten, W, while retaining excellent conductive metal to dielectric adhesion.